1. Field of the Invention
The present invention relates to an ESD protection device employing a MOS device and a latch-detected turned-on circuit, in which the MOS device comprises salicide process, to maintain the regular operating current in an inner circuit during an electrostatic discharge event.
2. Description of Related Art
Electrostatic discharge (ESD) is the major reason for electrical overstress (EOS) in electrical devices or an electrical system during operation. With the precision of the manufacturing process, the size of electrical devices is much smaller, so an unexpected electrostatic discharging event can break down the electrical devices. Moreover, the effect of ESD will cause a permanent damage of the semiconductor device or any other computer system for further influence of the electrical product.
It's extremely hard to prevent the human factor resulting in ESD. During the processes of manufacturing, producing, assembling, testing, depositing or even transporting, electrostatic charge accumulates in the human body, instruments, depositing equipment, or even the electrical device itself. In some conditions, an electrostatic discharge path will be formed to damage the electrical device or computer system unexpectedly since the contact event occurs between the human body and the equipment, or between devices.
For effectively preventing ESD damage to electrical devices, an ESD path provided by an ESD protection circuit is used to discharge the current formed from ESD events in the device. The largest electrostatic current affordable by a regular ESD protection device is associated with the second breakdown point of the device. The second breakdown zone B and the second breakdown point D of the device are shown in FIG. 1, which is the I/V characteristic curve of the ESD protection device. The ESD protection device will cause the permanent damage if the current formed from an ESD event reaches the second breakdown zone B. The conventional ESD protection circuit is implemented with an inverse-biased diode, a bipolar transistor, a MOS device, or a silicon-controlled rectifier (SCR). The aforementioned circuit components use their own characteristics of the first breakdown to discharge the current formed from ESD event. The first breakdown zone A is shown in FIG. 1.
If the current formed from ESD event goes through a first breakdown point C and reaches the first breakdown zone A, the ESD protection device operates on the snap breakdown zone E as shown in FIG. 1, in which the ESD protection device will not be destroyed by the current. Accordingly, the ESD protection device is grounded and forms an electrostatic discharge path.
A regular ESD protection device is set up in accordance with a human-body model (HBM) or a machine model (MM). Since the electrostatic current goes into the inner circuit from human body or the machine via the IC pins, the ESD protection circuit is conventionally disposed beside the bonding pad of the inner circuit.
Since the electrostatic charges in charged-device model (CDM) are accumulated in the floating substrate of the device, the electrostatic charges are discharged through the grounded pins by way of an ESD path. The devices of gate electrode in the input end is easily to be damaged when an ESD event occurs in a charged-device model even if there is an ESD protection device used therein. The ESD protection device of the prior art is still not capable of discharging impulse ESD current in the charged-device model, in many cases.
FIG. 2 of the prior art shows schematic diagram of an ESD protection circuit. The ESD protection circuit 20 comprises a primary ESD clipper circuit 22, a secondary ESD clipper circuit 24, and a resistor 26. The resistor 26 connects with the secondary ESD clipper circuit 24 in series. The resistor 26 and the secondary ESD clipper circuit 24 connect with the first ESD clipper circuit 22 in parallel. An ESD protection circuit 20 disposed beside an input pad 29 is used to protect inner circuit 21 from the ESD current 25, which is shown as a dotted line (25) in FIG. 2 and produced by ESD voltage 23 input from outside. The ESD protection circuit 20 is used to prevent the inner ESD current 25 from damaging an input-stage CMOS 28 composed of PMOS and NMOS, and guide the ESD current 25 to ground 27.
If the ESD in a human body model or in a machine model occurs on the pins of the input pad 29, the ESD voltage 23 with high potential from outside is transmitted to the gate electrode of the input-stage CMOS 28. The major function of the secondary ESD clipper circuit 24 is used to restrain the high voltage input from the ESD voltage 23, and to prevent the gate electrode of the CMOS 28 from being damaged by the high ESD voltage.
The secondary ESD clipper circuit 24 is implemented with a short-channel NMOS in general, but that implementation is not capable of enduring a large ESD current 25, so the extra resistor 26 and the primary ESD clipper circuit 22 are provided to keep the ESD current 25 from the secondary ESD clipper circuit 24 composed of a short-channel NMOS.
Since the ESD current 25 is discharged through the primary ESD clipper circuit 22, the circuit 22 requires a protection device with a higher capability for current endurance. Moreover, the aforementioned devices possess a higher breaking voltage and a slower breaking speed, so the secondary ESD clipper circuit 25 is further required to protect the gate electrode of the CMOS 28 efficiently.
Nevertheless, the ESD protection circuit 20 of the prior art can be equivalent to the combination of the larger resistor and capacitor, and work in the snap breakdown zone E next to the first breakdown point A shown in FIG. 1. Conversely, to the input signal, a larger RC time constant delay is produced, and thus ESD protection circuit 20 is not suitable for high-frequency signals and current-mode input signals.
With the advancement of manufacturing processes, the process with light doped drain (LDD) and silicided diffusion is employed. Although the density and performance of the IC is improved, the problem of ESD protection is also amplified.
For improving the of ESD protection capability produced by the manufacturing process with light doped drain (LDD), an ESD-implant process is employed. Two different NMOS devices are produced in a unique manufacturing process of a CMOS; the devices with LDD structure are used for the inner circuit and the devices without LDD structure are used for the input/output stage. For merging the two NMOS devices mentioned above into one manufacturing process, the mask used for ESD-implant process and some extra processes are added. Further, since the NMOS device produced from ESD-implant process and the device with LDD structure are different, extra treatment and design are needed to retrieve the SPICE parameter of the NMOS device with ESD-implant process.
With regard to the manufacturing process, the process of the silicided diffusion mentioned above is used to reduce the parallel stray resistance in drain and source electrodes of the MOS device. The operating speed of a MOS device can then be enhanced for achieving the high frequency application. Since the stray resistance of drain and source electrodes of the MOS device have been reduced by silicide process, the ESD current is easily guided to the LDD structure of the MOS device and causes the MOS device to be damaged. Even an output-stage MOS device with a larger size cannot enhance the ESD protection capability thereof.
A process of silicided diffusion blocking has been developed in the manufacturing process of the prior art for efficiently enhancing the ESD protection capability, in which a silicided layer is eliminated from the output-stage MOS device for raising resistance of the source and drain of MOS device therein.
FIG. 3A is the schematic diagram of a MOS device of the prior art, in which a plurality of source contacts 32a and 32b are included in an upper metal layer 31a and an under layer 31b, respectively, and further a plurality of drain contacts 33 is disposed in the midst of the MOS device. Moreover, a poly gate 34 is disposed therebetween for the purpose of current limitation.
FIG. 3B shows the drain with a silicide block of the MOS device. The space between drain contacts 33 and source contacts 32a, 32b should be of a suitable size for placement of the silicide block 35. The silicide block 35 is used to increase the resistance between the drain contacts 33 and the poly gate 34 to limit the current passed by, which enhancing the ESD protection capability of the MOS device meanwhile. Nevertheless, since the space between the drain contacts 33 and source contacts 32a and 32b becomes larger and the space occupied by MOS device increases in FIG. 3B, the number of the MOS devices that can be located is limited. In addition, the resistance increment of the device will increase the RC time constant delay of the input signal, which is not suitable to the input process of the high-frequency signal or the current signal.
Reference is made to FIG. 4, which shows an ESD protection circuit of an inner circuit disclosed in US Publication No. 2002/1030390. Both an ESD circuit 40 and an inner circuit 42 electrically connect with at least two wires 43, 44, which are a power supply cord and a zero potential cord, respectively.
The ESD circuit 40 includes an ESD protection circuit 410 between the wires 43, 44, and the ESD protection circuit 410 further includes an inverter 412 and a RC delay circuit 413. The ESD current produced from an ESD event can be discharged via an ESD path, which is formed by the forward-bias diode pair including diode D1, D2 or diode D3, D4, or by a substrate-triggered MOS 417 of the ESD protection circuit 410 operated in first breakdown zone A or the snap breakdown zone E. The CMOS inverter 412 is used to trigger the substrate-triggered MOS 417, and the gate thereon connects with the wire 44 via a resistor R2, which is to keep the substrate-triggered MOS 417 turned off when there is no ESD. The aforementioned ESD protection circuit 40 disposed between an input pad 45 and an inner circuit 42 provides the ESD path. The diode pairs including the diodes D1, D2, D3, and D4 are equivalent to the capacitors C1, C2, C3, and C4. The capacitor pair C1 and C2 is connected in parallel with the capacitor pair C3 and C4, and the equivalent capacitance decreases as the number of diodes increases.
Furthermore, even if the substrate-triggered MOS 417, the CMOS inverter 412 and the RC delay circuit 413 are included in the ESD protection circuit 40 shown in FIG. 4, the silicide block 35 shown in FIG. 3B is still needed.
When the silicide block is placed in the MOS device, it actually can enhance the ESD protection capability, but its equivalent resistance will also affect the performance in high frequency. Meanwhile, since space occupied by the silicide block becomes bigger, the number that can be set on a wafer is limited.
For improving the drawback due to the conventional ESD protection circuits, the present invention provides a device without the silicide block used in prior art, and still maintains the regular operating current in an inner circuit when electrostatic discharge (ESD) occurs.